31 Oct
2010
31 Oct
'10
8:21 a.m.
Johnny Billquist wrote:
Apollo [...] Using their own designed MMU (there were
none from
Motorola for the 68000),
The MC68451 was an MMU for the MC68000/010/012. It
didn't use
fixed-size pages, but it definitely was an MMU.
If you had implemented instruction restarts instead,
you would have
had to introduce a bunch of new registers in the CPU that kept track
of partial modifications done before the trap, so that you could undo
them before restarting the instruction. [...] With instruction
continuation, it's all preserved internally in the CPU without
exposing the software to anything new.
With instruction continuation, it most definitely was not "all preserved
internally in the CPU"; if that were done you'd be in big trouble if you
did a context switch to another process then it got a bus error also.
On the MC68010/012/020/030, when a bus fault or address fault happened,
a big block of internal CPU state was puked onto the stack. As a
consequence, the stack frames used for all exceptions (not just bus
error and address error) were different than those of the MC68000/008.
That most definitely does expose the software to something new. An
operating system for the MC68000/008 generally could not be used on the
MC68010/012/020/030 without modification.
Alternatively, instruction continuation could have left the partially
completed instruction state in programmer-visible special registers, as
was done for instruction restart in the high-end PDP-11 models. Then
the software could either handle the page fault immediately, or save
those register on the process stack or in a process control block, and
handle the page fault later.
On a CISC, there's a potential problem with instruction restart, which
is that if there aren't enough free MMU pages available, you can get
into a situation where an instruction can never complete execution.
When you try to execute it, you read the first word of the instruction,
but get a page fault reading the second word of the instruction which is
in the next virtual page and not resident. The page fault handler may
page out the page containing the first instruction word, and page in the
page containing the second instruction word, then try to restart the
instruction. Now it gets a page fault when reading the first
instruction word. This is a trivial example, but on a complicated CISC
an instruction may have to touch a lot of pages (on the order of a dozen
in some cases), and if the software doesn't map them all simultaneously,
the instruction can never execute to completion.
With instruction continuation, as long as the entire processor state
relevant to the partial execution of the instruction is preserved (as is
the case on the MC68010/012/020/030), even a complex instruction
touching many pages can continue to make progress as long as at least a
single MMU page can be devoted to the process.
Eric