26 Sep
2005
26 Sep
'05
10:43 p.m.
When connecting DRAM chips to the pins of a SIMM (i.e. laying out the
traces) does it matter if the order of the address and data lines is
preserved? In other words, does A0 on the SIMM need to connect to A0
on the chip, and A0 on all the other chips as well? These are old
DRAM, such as FPM or EDO, used in 30 pin SIMMs. Nothing new and
fancy like SDRAM.
Well, obviously for plain read and write, you can scramble the address
and data lines any way you like (provided, if there are separate DIn and
Dout, that you keep those consistent).
There are a few possible problmes.
1) Refresh. If you use CAS-only refresh, then it doesn't matter at all,
because the DRAM chip generates the refresh addrees. If you use RAS-only
refresh, then it shouldn't matter as to the order uless only some of the
address lines are used for refresh. For example, some 64K DRAMs (8
address lines) only used the lower 7 for refresh, then you would have to
keep A0-A6 on the system going to A0-A6 on the RAM _in some order_, and
keep A7 linked to A7.
2) If there are any clever multiple read modes, it may well be that you
can do things change the bottom 2 address bits without doing a full
memory cycle and effectively read 4 locations per full memory cycle. If
the RAMs support something like that _and your machine uses it_, you'd
have to keep A0 and A1 wired to A0 and A1 of the DRAMs.
-tony