FPGA VAX update

Hello fellow ClassicCmp'ers, I have made it known in the past that I have interest in designing and building a new CPU chip implementing the VAX architecture (just as DEC would have made a new implementation of the arch from the spec, not a clone of any particular past implementation), and since I don't have the $$$ to fab a real chip, it'll be a "soft chip" in an FPGA at first. This project has been on my mind for a long time, mostly far on the back burner, but some other life circumstances have recently dragged me once again into the fun world of FPGAs and HDL coding (I'm doing a consulting job that involves lots of FPGA work), and this circumstance has brought my FPGA VAX project back closer to the front of my mind. Obviously there are tons of issues involved in a project of such ambition, and I don't want to bore you all to death talking about all of them, but the one issue that I have a difficult time solving on my own is that of FPGA tools. I'll be using Icarus to compile Verilog to EDIF. I have heard sermons non-free designs with non-free tools) about how inferior it is compared to whatever non-free shit they use, but I don't care, freedom is more important to me than quality. (And I mean free as in speech, not as in beer.) The problem is of course with place & route and the actual FPGA bitstream or SOF (SRAM object file) generation. The first part of the problem is that the fucking FPGA vendors won't give us a complete description of the FPGA routing fabric and bitstream/SOF format. The second part of the problem is that even if this information were pried out or reverse- engineered, someone would still have to write an open source P&R tool, which is a *major* task - certainly not for me, designing a VAX CPU is enough work for me, I don't need the extra task of developing an FPGA P&R tool. There are only two practical choices when it comes to the actual target FPGA: A or X, which of course stand for Altera and Xilinx. I would be content with either if I could work out a usable toolchain for it that would take me from EDIF (Icarus Verilog output) to the SOF or bitstream file (A/X respective terminology). To make the long story short, there are two specific areas where I could use help from other listmembers: 1. The Xilinx option. The maintainer of Icarus Verilog only has experience with Xilinx. He uses X's proprietary P&R tools, but they are command line tools and are available for Solaris and Linux in addition to Losedows. (I still can't figure out whether the Xilinx-blessed Linux version is truly native or runs through WINE.) Icarus documentation includes a complete worked-out example of a build starting from Verilog and ending in a bitstream, feeding iverilog output (EDIF) to the command line tools from X's proprietary software. Since this might be a workable option for me, does anyone here have the Xilinx Foundation tools installed on a Solaris or Linux box on which I could get an account for work on my FPGA VAX project? 2. The Altera option. The company for which I'm currently doing the consulting project that brought me back into the FPGA world uses Altera, so I have an Altera FPGA dev board and their fucking Quartus II software. I still haven't figured out whether there is any way to use the latter without the GUI, however, and I only have the Losedows version currently and WINE isn't exactly my cup of tea. So I don't know if I'll be able to shoehorn Quartus into a backend for Icarus Verilog like the good maintainer did with Xilinx Foundation. However, one coworker tells me that he has seen an open source project that apparently reverse-engineered A's SOF format and can make an SOF that made me salivate. The problem is, however, that this guy (my coworker) does not remember the project name, much less its home page, and I have looked for it without success both on the major open source hardware sites and with Google. The feat sounds so incredible that it may just be too good to be true. My coworker said that he'll look for it on his Linux box at home. But barring that, has anyone else heard of this project? TIA for any help, MS