bit-widths, was Re: HP Laserjet ..again....

Tom> ... and many did not. The 'byte' as a convention for talking Tom> about memory is just that, a convention, and fails miserably on Tom> machines whose major casual metric is not a multiple of 8 Tom> bits. Many, many machines were built on a multiple of 6 bits Tom> because that's how many it took to define a character. Tom> For machines which have some architectural feature > 8 but Tom> modulo 8 == 0, 32- and 64-bit wide memory and paths could be Tom> byte-addressed. I don't know for sure, but I would imagine there Tom> are 6-bit-character-addressable instruction sets too. In some sense, you could say that of the Burroughs 5000/6000 series. Those had character pointers, though most of the memory addressing was to 48 (or 51, if you count the flag field) bit words. How about the IBM 1620, with digit-addressable memory, 5 bits plus parity per addressable entity? Tom> Until more or less when CPUs fit entirely within silicon, there Tom> was no hard and true correlation between the bit-widths of Tom> busses, registers and paths; this was because constructing those Tom> things cost actual money and scaling of silicon didn't Tom> exist. Lots of machines have different width regs/accumulator, Tom> memory, index regs, program counters, arithmetic units, etc. Tom> (My LGP-21 is a good example: 32-bit accumulator, 31-bit memory, Tom> 12-bit program counter, double-32 product reg, 4- or 6-bit I/O.) Or the CDC 6600 CPU: 60 bit memory, some 60 and some 18 bit registers. In the PPU: 12 bit memory, 18 bit accumulator. If you count the link bit, the PDP-8 has a 13 bit accumulator I believe. Tom> For non-multiple-of-8 machines, the 'byte' is not relevant Tom> generally. ...though the term might be used to describe a 6 bit chunk, or a 12 bit chunk (CDC), or a variable width chunk (PDP-10). paul