12 Jun
2009
12 Jun
'09
11:21 a.m.
On Jun 12, 2009, at 11:47 AM, Guy Sotomayor wrote:
On Jun 12, 2009, at 5:04 AM, Brad Parker wrote:
Very Cool. I did a "direct decode" pdp-11 in verilog recently just to
see how big it would be (and because I was frustrated with the pop-11
project). It fits nicely & boots RT11 at 50mhz. Passes diags except
for the
11/34 diag which assumes (r)+ doesn't happen if there is a trap.
One thing I did (following pop-11) was to make a "rk11" register set
which actually talks to a IDE disk.
I love microcode but these days fpga's are so big direct decode is an
option.
http://www.heeltoe.com/software/pdp11/
-brad
Guy Sotomayor wrote:
>
> Actually one of the guys I work with has done an FPGA design of a
> PDP-10. He's partitioned it into 3 Xilinix parts. It passes all of
There is *no* micro-code (unless you want to count Verilog) - it's
all logic. I don't know much about his design other than what I've
mentioned above.