17 Aug
2006
17 Aug
'06
5:39 p.m.
On Aug 17, 2006, at 7:39 PM, Tony Duell wrote:
There were a lot of myths about how critical the
layout was with DRAM
(and Rainbow printed some of them). Yes, you do need to take care. It
is
a high-speed circuit, you should try to keep traces the same length,
decoupling is _essential_ as is a low-impedance ground track. But to be
honest, making an SRAM board that runs at the same speed is no easier.
From 1986 to early 1988 I worked on the Navier-Stokes Supercomputer
Project at Princeton University. Each node of that machine had four
4MW memory planes (36-bit word) built from 41256 chips; 576 chips per
memory plane, handled by a pair of Intel 8207 DRAM controllers. We had
really nasty problems with the refresh cycles creating tons of noise on
the Vcc bus. Man that was a nightmare; it took weeks to get it cleaned
up. If I recall correctly we wound up rebuilding the boards with a
bypass capacitor for every DRAM chip.
Incidentally, that computer was built in DEC OEM chassis of the same
style used in PDP-11/24 and /44 systems. DEC sold those chassis
unlabeled, along with optional blank backplanes, for customers to build
whatever they wanted to...DEC-machine related or not, computer-related
or not. We used the DEC backplanes and built our boards in the Unibus
form factor.
-Dave
--
Dave McGuire
Cape Coral, FL