27 Feb
2013
27 Feb
'13
2:06 p.m.
Am 27.02.2013 20:57, schrieb David Riley:
There are a lot of discrete or paired FETs that should
do the job of the
driver quite adequately;
I had that idea, too. Even easier to design and -
cheaper.
the receiver is usually best done with a high-speed
comparator, which unfortunately tend not to be particularly cheap. The best
one I've found for modern devices is the MAX9108, which fits the required
35ns propagation delay;
35ns is not that fast. But it could work.
it has TTL outputs (not great for 3.3v logic, but you
can use glue) and costs about $1 per gate ($.50 per in>= 100 qty).
The CPLD
I'm planning to use (the three small ones are result of an "accident"
when estimating the pin consumption) is 5V tolerant.
I will keep the current design for now. After building a prototype of the final
board, I'll simply test it in a really loaded 8/e. And then we'll see if there
are reliability issues. I'll also test the system with the card in place.
Philipp
--
Dipl.-Inf. (FH) Philipp Hachtmann
Buchdruck, Bleisatz, Spezialit?ten
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Fax. 0511/3500439
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