20 Oct
1999
20 Oct
'99
3:28 a.m.
allisonp(a)world.std.com wrote:
[snip]
ok, By discrete you meand transistors and diodes.
An 8080 cpu would likely fill a rack 20-25" high with boards.
The memory would have to be core for practicality as a static FF cell
uses lots of transistors and would be huge. using core 64k would likely
fill one or more 6" racks (using 1967ish technology). A uart would fill
a 9x11 board with TTL and that would expand to maybe 4-5 boards as
transistors/diodes.
Using discrete transistors to build flop cells on that scale would be so
large that getting the timing to work would be a real pain. Core wouldn't be
bad at all; mid 70's core technology stuffed 32K * 20 in an 8" x 4"
area with no sweat; drivers and transceivers wouldn't double that.
I have trouble with the notion of the uart filling a 9 x 11 board given
that I'm holding one that's occupying 4 x 5 inches in SSI. Yeah, the shift
registers would take a bunch of space but I don't see it using anywhere
near the amount of real estate suggested.
In truth, since clock speed in such a beast is going to be low, dissipation
isn't going to be an overriding factor. The upper limit on flop density is
going to be how tightly we can physically pack the stuff, which is going to
be markedly higher than in the '60s. Discretes of similar functionality
are much smaller and we have routing tools which allow us to make use of
multilayer boards while our '60s compatriots were laying stuff out by hand
on light tables (been there, done that, never again).
A pdp-8 (early) had a pannel roughly 24"x50"
with flip chip modules mostly
transistors and the 4k core was a 10" tall rack section. for rough
comparison. In many respects the 8080 is a far more complex CPU and would
be significantly bigger. It would also be slow compared to the NMOS part.
I suspect you could build a pdp-8 using contemporary layout tools and discrete
technology that, excluding the core stack, was an order of magnitude smaller.
Using '70s core technology you could get the stack somewhat smaller while
increasing the storage density by a factor of eight. The 8080 would without
a doubt be larger than the '8 and slower than the NMOS version of the chip;
it would also cost a fortune to build.
Doing it in ttl or bit slices would still be big,
I've done that. using
2900 parts(ca mid to late '70s) the CPU equivelent was over 100 chips and
filled 4 10x8" cards.
That sounds about right; I recall building a PDP-11 clone using 2901/2910 parts
as part of an undergraduate CPU architecture course in the same era and using
about the same number of parts. Of course you can make most of the chip count
go away by tossing a single (small!) xilinx chip into the mix.
Best,
Chris
--
Chris Kennedy
chris(a)mainecoon.com
http://www.mainecoon.com
PGP fingerprint: 4E99 10B6 7253 B048 6685 6CBC 55E1 20A3 108D AB97