15 May
2014
15 May
'14
8:36 p.m.
On 2014-05-15 14:50, David Riley wrote:
On May 15, 2014, at 1:47 PM, Keith Monahan <keithvz
at verizon.net> wrote:
Huh? You apparently don't know what a PSoC is. It's a hybrid
programmable logic device and micro-controller. There are several
programmable logic blocks called UMBs inside the PSoC - each roughly
equivalent to a 22V10 SPLD. A PSoC has more macro cells than many CPLDs
and by far more data pump logic to/from the rest of the device. And the
micro-controller side is a "real microcontroller" - in fact the same
micro-controller core as your STM32 - an ARM Cortex M3. It does have a
proper multi-bit SDIO core, however it requires logic support from UMBs
and there may not be enough left over after the SCSI data pump.
Yes, I agree a discrete CPLD/FPGA + STM32 would be better performing
solution, however it would be more than twice the cost of a PSoC 5 in
just those ICs alone. I don't agree a standalone STM32 having to
bit-bang the SCSI side would perform better. Michael did a fabulous job.
I had started a design like it that evolved from a MachXO2+SiLabs M3
into a single PSoC 5, but Michael beat me to the finish line.
-Alan
I tested the data rates from an ubuntu PC with an
adaptec card, and I was getting between 720KB/s - 820KB/s. This is slower, but there's
room for optimization via software upgrade. (and even higher speeds available with newer
uC or FPGA, if there's a future version)
I don't think an FPGA is really necessary to maximize the speed (though a simple CPLD
or one of the really tiny FPGAs they're calling CPLDs these days might be a boon for
sync mode). However, I would love to work with the guy to bring it to a real
microcontroller that has a proper multi-bit SD controller and external bus interface, like
one of the STM32 family, instead of those dreadful PSoC chips. Maybe I'll drop him a
line...