segmented memory models

No, not as a single chip (AFAIK). But that doesn't stop somebody building one if they want to. And AFAIK there is no MMU for the PDP11/20 (the first PDP11 implementation). And yet it got the extension of 16 bit program addresses to 18 bit bus address 'correct' ((a) what all other 11's do and (b) what was sensible to do given the fact that I/O devices sit at the top of the address space)/ IIRC, it's not strictly a vector, in that that location doesn't contain the address of the routine to be executed on Reset (as is the case on, say , a 6502 or 6809), but rather the first instruction to be executed. But anyway. No, I don;t think putting the reset at the top of memory was inherrently silly. It's just that it doesn't seem to have served any real purpose. The problems on the 8080 systems caused by having reset jump to location 0 were really due to the fact that reset jumped to a fixed location, not where that location was. So moving it somewhere else neither helped nor hindered anyone. And that's where I disagree. The addreess FFFF:0000 can _also_ be interpretted as '16 bytes below the physical top of memory. Given that the reset routine is likely to be in ROM, and given that contiguous RAM is generally a good thing, IMHO it would have been better if the physical address outputted by an 80286 for the first instruction after reset was FFFFF0 (not 0FFFF0). One way to do this would have been similar to the PDP11 I/O address trick (which is why I brought that up), namely that in real mode, the 'extra' 4 address lines of the 80286 (over the ones of the 8086) are all set to the same state and that state is the logical AND of the top so-many-bits of the current segment register. -tony