1 Jun
2009
1 Jun
'09
3:52 p.m.
dwight elvey schrieb:
Hi
Does anyone have a nice pointer to a diagram
of how the 68K bus is to be connected to RAM?
I not that familiar with all the various signals.
I've spent some time searching but maybe don't
have the right search string.
Dwight
Google search string may be "68000 schematics", and it will point to the
first link
of "68k Single Board Comupter" from "....ac.th" which hides the
interesting part
in a CPLD, but the second link will lead to a detailed PDF
http://www.chiark.greenend.org.uk/~theom/electronics/has/ha68ksys.pdf
which describes the stuff.
Basically, you can derive the relation of UDS, LDS, R/W, AS and DTACK
from the
data sheet, for interfacing RAM the
trick part is just the generation of
DTACK;
as long as CPU clock and RAM access time is known, it is a straight forward
wait state circuit.
--
Holger