10 Apr
2007
10 Apr
'07
3:12 a.m.
On Tue, 10 Apr 2007, Philip Pemberton wrote:
The data separator is an Verilog HDL reimplementation
of the data separator
used in Petr Simandl's Sinclair Spectrum +2A floppy disc controller
(<http://www.simandl.cz/stranky/zxs/obrazky/zx_radic_89k.jpg>, but there's a
better quality schematic at
<http://www.worldofspectrum.org/BackToThePlus3/>). I'm driving the whole
thing off a 32MHz TTL oscillator, divided down to 16MHz for 3.5" DSHD, and
8MHz for 3.5" DSDD. I haven't tried FM encoded data yet, though I have no
reason to suspect it won't work, as long as I can figure out what the clock
divider needs to be set to.
Stupid question: where is the PLL? Is this a digital PLL built around the
SN74188? Isn't that only the data separator, i.e. detection of data
windows, which is then MFM only? This design looks a bit too
primitive...
[...]/hpla-fdd-reader-syncing-against-720k-floppy-zoomed-long.png
Hmm, /RDDAT, DWIN and DATA don't look right to me. You seem to generate
DATA bits during clock time. Is /RDDAT coming from the floppy and is DATA
going to the FDC?
/RDDAT shows the bit pattern 10100001, i.e. $A1. But the address mark for
MFM consists of four bytes ($A1A1A1xx), and the address mark bytes have
clock bits 2, 3 and 4 removed, your data stream seems only to have bit
3 removed.
But it's possible that I just don't fully understand this design.
Christian