30 Aug
2009
30 Aug
'09
1:58 p.m.
Greetings all;
In my continued efforts to try and get my 11/34a functioning I decided to
set up my logic analyser and trap ALL of the 56 Unibus signal lines to see
if I could spot anything that was being held asserted when it shouldn't.
For reference, my 11/34a is set up like:
1 M8266 -------------------------------------------|
2 M8265 -------------------------------------------|
3 M9301 YJ-----| FLIPCHIP
4 M7856---------------------------|
5 National Semiconductor Memory Board--------------|
6 G7232---------|
7 G7232---------|
8 G7232---------|
9 M9302--------| G7232---------|
I only have the basic front-console, so not the lovely button-filled
operators console. All the NPR jumpers are in place. All voltages check
out.
The symptoms are:
Unit powers on, RUN light comes on and then quickly goes out. When the
BOOT/INIT switch is toggled, again, RUN light on, then out. Clearly the
unit is HALTing on something, but I can't work out what and nothing seems
to appear on the console.
When I analyse the bus the unit follows what, from the Unibus design
manual, appears to be a standard start-up procedure.
- All signals float (obviously)
- All signals cleared, DCLO/ACLO/INIT asserted
- 773000 is placed on the Address lines (as configured in the bootstrap)
- DCLO negates
- ACLO negates
- INIT negates, and then immediately:
- Address lines are cleared
- SACK is asserted
I find no mention of SACK being asserted in the Unibus manual in its
start-up section. Furthermore, as my understanding goes, SACK should only
be asserted when a bus master has accepted a grant and is beginning a
transaction cycle. There is NO activity on the request/grant lines, so
nothing should be allowed to become bus master, so I think this SACK
signal should not be happening.
Can anyone with more understanding than me (which, you know, is pretty
much everyone else who owns a PDP11) confirm I'm not completely off-base
here?
I have two M7856s and have switched between them, so if it's the 7856
that's holding SACK, then both of mine are doing it. Elsewise... I think
the only thing that could be "sticking" is the processor boards, as the
memory card shouldn't be able to assert SACK since it can't become a bus
master. If this guess is correct... I'm not really sure how to begin
debugging what on the processor board is getting glued. Time to break out
those schematics?
My thanks to all for your thoughts;
- JP