31 Oct
2001
31 Oct
'01
2:15 a.m.
Richard Erlacher wrote:
What's different is that the style of design that was used back when the
classics were being worked out was so different from what's done today. Back
then, fully synchronous design meant that all the devices used were of the same
technology and that meant cost impacts whenever fully sunchronous rather than
locally asynchronous, globally syncrhonized structure was used, since that meant
that a nand gate had to have two dual-rank registered inputs and a registered
ouput. Which immediately raised the cost of that 30-cent gate to $4.80. Back
then arrays were a sea of gates, and things changed depending on which gate of
the 4000-6000 identical nands in the array you were using.
Never used the stuff. Since they don't make TTL any more I kind was
forced into using
FPGA's. :). Also a FPGA prototype board is cheaper than 150 new TTL.
Mind you now
that I got the FPGA working TTL looks better since I don't have to burn
PROMS.
Of course the problem that 74LS382's and 16x4 non-inverting ram don't
exist today
does make life difficult.
Well, there's a wide gap between core memory, and the designs of the era (pre
'72) when it was common, and the '80's when fully synchronous design became
the
order of the day.
Another thing to keep in mind is that most CPU's of yesteryear are not
integrated circuits, but, rather, board(s) full of the them. I remember looking
at a 16-bit CPU from some Florida company that was being customed up by my then
local circuit house and it occupied a 22x32" panel (very large for the time) of
5-layer circuit board, all in STTL. The outer layers were intended not so much
for containing the RFI as for dissipating the heat, to wit, the entire long
outer edges of the board was mounted to a 3-1/2" square heatsink that drew heat
from the board and had fans attached specially provided to manage this board's
dissipation requirement. It was quite a thing to behold!
And POWER was cheap.
<snip>
Not all CPU chips of yesteryear were even built with
clocked logic. If you look
at the ones with a single clock cycle for a single bus cycle, e.g. 6800, et. al,
you'll find that the clock was a useable as a steering member and a timing
reference, but not necessarily a clock to a set of registers. I'd say FlipFlops
of the R/S and transparent latch sort were much more common than those used for
counting. In fact, I recently revisited the 650x core recently and found that
it could and probably should be built with no clocked flipflops at all, using
the ALU to increment the PC and stack pointer as well as operating on the data
registers. That's what reduced the poundage of silicon in the 650x series
chips, which, aside from their very elegant instruction set, is what bought them
their market share.
Playing around with a TTL style cpu design in a FPGA I found I needed
lots of clock
enables but had I used real TTL I would of just generated the 4 or 5
clocks needed.
Like you said using latches saves about 1/2 the gates needed of a
Flip/Flop and
that saves a good bit. The 6800/6502 memory interface is nice. That is
the style I am
using on my FPGA.
Today, a small array
consists of a putative 100K gates, of which one's lucky to be able to get the
equivalent of 10K gates in actual practice. Of course they count a 3-input gate
as two gates and a 4-input gate as three, and a D-flop as over a dozen, rather
than the 6 it should really use. Then there's that LUT, which , to the
marketing department represents a lot of logic, even though you have to use the
whole thing just to make a single 5-input AND. Consider how much of the
marketing departments resources you consume with what would have been a 74S133.
100K gates Ha! LUT's tend to be really wasteful of multiplexes. A 4-1
multiplexer is
3 logic cells. Mind with the stupid marketing works you can't get the
small
and easy to work with FPGA's cheap but you are expected to buy the large
and
painful chips for $$$. All of my FPGA work is a hobby so I have to stick
to 84
PLCC packages that nobody wants to sell. I like anti-fuse FPGA's idea of
you power up
and go. Reminds me of TTL :).
Well, if you put pencil to paper before the
instruction set is defined, and
before the requirements are firmly defined, you're wasting time, and, sadly, I
doubt that many CPU designs start on a clean sheet of paper these days. They
certainly didn't back in the "old days." There's always the political
baggage.
That is true there is baggage.My two gripes today are
1) No bootstrapping a minimal system in hardware & software - you need
everything to run.
2) Non serviceable equipment and docs.
Ben Franchuk.
--
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.