Micropolis 1203 Re: Reviving a PERQ 1a

Then, if it's from a PERQ at all, it's from a PERQ 2T1. The PERQ DIB (Dsik Inteface Board) fitted on top of the track side of the main logic board on the drive. Other htan that it's a standard 1203. Many years ago i managed to borrow the 1203 service manual. I have no diea where from (it may have been one of the departments of the university where I was studying). What I do know is that at the tiem scanners were unheard-of, I didn't have my own copier, and copying in the deparment was non-triival. Therefore I couldn't make a complete copy of the manual. What I did do was copy the bits I thought were non-obvious (to me) -- the schemnatics, error codes, etc. And produced my own parahprase of the tehory-of-operation sections, leaving out the vry obvious bits, like the microcotroller + ROM.. I've found those files on this machine, I will include them at the end of this message. There is a LaTeX document (old LaTeX) for the interface signals and a text file giving the theory of the motor and servo sections. I cna problaby photocopy the schematics, etc nad have them scanned or send them to you if that wopuld eb any help. But not for the next week or so (personal reaosns). If not, I can send them again. I normally use a .tar.gz file. I can upload to an anonymous ftp site, or mail it (uuencoded or MIME attachment). Let me know... -tony -------------- \documentstyle[12pt,A4]{article} \begin{document} \section{Interface Connector} J1 carries the signals to/from the controller, while J2 carries radial signals (not controlled by drive select) and the LED signal.J1 is a 50 pin 0.1" edge connector with the following pinout \begin{tabbing} \=\hspace{0.5in}\=\hspace{0.5in}\=\hspace{1in}\=\\* \>Pin\>Ground\>Signal\>Desription\\* \>2\>1\>-\>Reserved\\* \>3\>-\>-\>Reserved\\* \>5\>4\>R/W Data+\>Read/Write Data\\* \>6\>-\>R/W Data-\\* \>8\>7\>DS1/\>Drive select MSB\\* \>10\>9\>DS0/\>Drive select LSB\\* \>12\>11\>Busen/\>Bus Enable\\* \>14\>13\>BA1/\>Bus address MSB (Register Select)\\* \>16\>15\>BA0/\>Bus address LSB\\* \>18\>17\>Enable/\>Interface Enable\\* \>20\>19\>-\>Reserved\\* \>22\>21\>Bus7/\>Data bus MSB\\* \>24\>23\>Bus6/\\* \>25\>-\>TV\>Terminator +5V\\* \>26\>-\>TV\\* \>28\>27\>Bus5/\\* \>30\>29\>Bus4/\\* \>32\>31\>Bus3/\\* \>34\>33\>Bus2/\\* \>36\>35\>Bus1/\\* \>38\>37\>Bus0/\\* \>40\>39\>Rdy/\>Drive Ready\\* \>42\>41\>Flt/\>Drive Fault\\* \>44\>43\>Iladr/\>Illeagal address\\* \>46\>45\>Skcmp/\>Seek Complete\\* \>48\>47\>Idx/\>Index Pulse\\* \>50\>49\>Secp/\>Sector Pulse\\* \end{tabbing} The RW Data balanced line should be terminated into 68$\Omega$ at the controller, while the remaining signals should be terminated by 220$\Omega$ to +5V and 330$\Omega$ to Ground. J2 consits of a 2*5 0.1" Header plug. Pin 1 is on the J1 side of the connector, away from the PCB. The pinout is given in the next table \begin{tabbing} \=\hspace{0.5in}\=\hspace{0.5in}\=\hspace{1in}\=\\* \>Pin\>Ground\>Signal\>Desription\\* \>2\>1\>Rdy/\>Drive Ready\\* \>4\>3\>Skcmp/\>Seek Complete\\* \>5\>-\>+5V\>Power for LED\\* \>6\>-\>Sltd/\>Drive selected status\\* \>8\>7\>Idx/\>Index Pulse\\* \>10\>9\>Secp/\>Sector Pulse\\* \end{tabbing} These signals are not controlled by the Enable/ or Drive Select signals. \section{Interface Signals} \noindent {\bf Enable/} The enable signal enables the interface on the drive when it is the active low state. It may be used as a powerOK signal to prevent the drive if the interface cable is removed. \noindent {\bf DS*/} These signals form a 2-bit binary coded drive select input, allowing up to 4 drives on the same cable. The drive address is selected by a jumper on the drive logic board (W3-W6) near U17. The signals on J2 are not controlled by the drive select. \noindent {\bf BA*/} These signals form the address inputs to allow one of 3 registers in the drive to be selected. The addresses are : \begin{tabbing} \=Address\hspace{0.25in}\=Register\\* \>0\>LSB cylinder\\* \>1\>MSB cylinder \& Head\\* \>2\>Control\\* \>3\>Not Used\\* \end{tabbing} \noindent {\bf Busen/} This line is the active-low bus strobe that writes data from Bus0--Bus7 into the selected register. The head and cylinder registers are loaded on the rising edge of this signal, while the control register can be loaded while the signal is low. \noindent {\bf Bus*/} These lines form an 8-bit data bus from the controller to the drive, with Bus0/ as the LSB. The bit definitions of the registers are given next. The LSB cylinder register contains the lower 8 bits of the cylinder address, with bit 0 being the LSB The MSB cylinder \& head register contains the upper 4 bits of the cylinder address in the high nybble, and the head select code in the low nybble. The head select code must be 0-4, and the cylinder address 0-579. Writing to this register causes a seek operation, and Skcmp/ goes false until the head is on the destination track. The control register contains 6 bits which control the operation of the drive. These lines are not latched, but are applied to the drive logic while Busen/ is true. The signals are as follows {\it Wen} (bit 0) This signal enables the write amplifier, causes the RW data signals to be inputs, and allows the drive to write when it is true. {\it TOP} (bit 2) {\it \& TOM} (bit 3) These signals allow the head to be offset from the centre of the track durint read operations. TOP (Track Offset Plus) moves the head 100 microinches towards the spindle, TOM (Track Offset Minus) moves the head 100 microinches towards the edge of the disk. {\it Frst} (bit 4) This signal -- Fault Reset -- resets the fault latch in the drive provided no fault condition currently exists. {\it Rtr} (bit 6) This signal causes the positioner to restore the heads to track 0. {\it Gain} (bit 7) This signal increases the gain of the read amplifier by about 20\% to allow the recovery of marginal data. \noindent {\bf RW Data}. This pair of differential signals is a bi-directional data transfer line between the drive and the controller. When Wen is true, this line is an input on the drive, and each rising edge of this line causes a flux transition to be written on the disk. If erased gaps are written (i.e. when Wen is true, and there are no transitions on the data line), then the maximum length is 4$\mu$s and the minimum spacing 40$\mu$s to prevent upsetting the read AGC circuit. In read mode (Wen false), this line is an output from the drie, and a pulse is output for every transition of the flux on the disk. The controller should operate on the rising edge of each pulse. \noindent {\bf TV} These pins may be used to supply +5V to the terminating resistors in the drive, so that the termination will reamin active even if the drive is turned off. \noindent {\bf Rdy/}. This signal goes true when the heads are loaded and no fault condition exists. Read, Write and seek operations are inhibited when Rdy/ is false. This signal goes active when the drive completes it's power-up sequence, and remains active until a fault occurs or the power fails. \noindent {\bf Flt/}. This signal goes active if a fault occurs in the drive, and remains active until a fault reset occurs (see above). The fault conditions detected are : DC power fault (one or more PSU voltages low), Spindle fault (spindle will not reach or maintain the correct speed), Positioner fault (Head could not seek or restore), Read/Write fault (more than 1 head selected, or write current exists when Wen is false), and Write Unsafe (attempt to write when head is not on a track centre). The first 4 conditions cause the head to be unloaded and the spindle to stop. \noindent {\bf Iladr/}. This signal indicates that the controller has attempted to seek to a cylinder larger than 579, or select a head not present in the drive. \noindent {\bf Skcmp/}. This signal indicates that no seek or restore operation is in progress, and that the heads are on the destination track \noindent {\bf Idx}. This signal goes true once/revolution to indicate the start of the track, and the falling edge should be used as a reference. \noindent {\bf Secp}. This signal goes active from 1-128 times/revolution to indicate the start of each sector. The number of sectors is selected by a jumper block on the drive logic PCB at location JX3. \end{document} ----------------- Micropolis 1200 Service Notes ----------------------------- These notes are known to be incomplete. In particular, the CPU section is omitted - if you can't figure out how that works, you shouldn't be fixing the drive! [Bracketed letters after IC designators indicate Drive Logic (l), Motor Control (m) or Preamp (p) boards. PSU --- +24V regulated down to +12v, and thence to +6.2V -12V regulated to -8V, and thence to -5V and -4V Relay K1 on motor board disables +6.2, -8 (Etc) regualtors until spindle is up to speed. K1 is controlled by Positioner Enable signal via U18b(m) K1 also limits spindle motor current via external resistor, removes power from Write Amp (to protect data) and Causes emergence retract (Dischages C31 and C32 through positioner coil to retract head assy). U1(m) (LM339) checks +5,+24,-12V rails in tolerance, and drives PSEN signal via Q1(m) and Q2(m) Comparator U10(m) monitors current drawn by preamplifer module, and activates RW Unsafe if this current is too high (either Vcc or Unsafe). RW Unsafe goes to logic board, and is inverted by U16a(l). It's then Combined wiuth Transient Blanking and Reset HD to produce RW Fault. The break solenoid current is monitored by Q4(m) and Q14(m). If sufficient break current is sensed, then Break Fault goes low, and the spindle motor is enabled via U11b(m). Spindle Motor ------------- System uses Optical comutation. Signals from phototransistors Q5(m), Q6(m), Q7(m) are processed by comparators U19(m) and U20(m). TTL outputs are then fed to U4(m) (3-8 decoder), the outpus of which are combined by U3 and U5, and then bufffered by U6 to drive motor drive transistors Q8-Q13. When motor is stopped, U5*(m) are all enabled by Enable Spindle being low. Hence Q9, Q11, Q13 all on, motor coils shorted out, so motor stops. When motor is accelerating, all transistor commutate as expected. When motor up to speed, IMS/ signal goes high, disables U4, so all transistors off. Motor runs due to inertia, until speed drops enough for IMS/ to go low. Speed control is 2-state (on/off) digital. U11a(m) and U13b(m) generate 470ns pulse for each rising edge of X phototransistor signal. This pulse Presets the 12 bit counter U14(m)-U16(m), which is clocked by 400kHz signal derived from the CPU ALE signal, buffered by U45d(l), U52d(l), and gated by U13a(m). Final (2048) output of counter is speed low signal. If speed is very low, U13c(m) is enabled, and counter is inhibited via U13a(m) Motor sequence : 0-2500 rpm : Positoner disabled, so U11d(m) inhibited. Thus U12a(m) is held set, and IMS/ signal forced low. Motor accelerates as above. Speed Pulse (X p/transistor buffered by U3d(m) is monitored by CPU to check for spindle faults. When speed gets to 2500 rpm, CPU asserts Enable Positioner/ signal. Thus U12a(m) is no longer forced into the preset state, and instead is loaded with speed low on each X pulse. Enable Positioner/ operates relay K1, and removes current limiting resistor from motor circuit. 2500-3600rpm. On rising edge of X, speed low is high. Thus IMS/ is still low, and motor still accelerates. @3600rpm. Speed low is low when X rises. So U12a is cleared, and motor is disabled by IMS/ signal. Motor runs due to intertia until speed drops enough for IMS/ to got low again. If motor speed drops too much, U13c(m) is enables, and counter is inhibited. Then U12b(m) (speed OK flip-flop) is reset. This flip-flop was set by rising edge of IMS signal from U12a(m). Output of U12b(m) is fed to CPU and interrupt logic. Position Servo -------------- Servo head signal amplified by U1(p), and fed to drive logic board. Signal is then amplified by U19(l) and filtered by LC filter (L8(l), L9(l), etc). Output is then buffered by Q20(l). Gain of U19(l) is controled by FET Q19(l), which is controlled by the AGC circuit. The output of Q20(l) is fed to peak detector U29a(l) [GS/ signal is always low, so Q26(l) is always on], and the output of this is fed to the limited gain integratopr U29b(l). This integrator integrates the diference between the peak servo voltage and the reference set by R144. The non-inverting imput of U29b(l) is driven by a DC voltage which is essentially the temperature compensated (by U79(l)) level of the servo signal. The output of the integrator controls the gain of the servo amp via FET Q19(l). The servo signal is sampled by the GA/ and GB/ signals from the servo control logic by FET's Q22(l) and Q24(l). The peak value is stored on the hold capacitors C111(l) and C114(l) and appears as SA and SB at the outputs of U32a(l) and U32b(l) repsectively. Raw servo signal is applied to peak-detector latch U39(l), which detects the servo pulses. Gates U11b(l) and U69b(l) allow servo PLL to open during spin-up to prevent it locking off-frequency. When the servo is enabled, the circuit operates normally. Sync Gate/ from the PLL PROM provides noise imunity by only allowing U39 to operate near the expected sync position. Sync detector U65b(l) and U54b(l) detect pairs of sync pulses, and provide one sync pulse (on TP9) for each sync pair. This pulse is stretched by U65a(l) (critical 1.39us adjustment on R157), to provide reference for PLL U64(l). U164(l) operates with counter U63(l) to provide a 16* servo burst frequency, and thus provide sampling clocks inside each servo cell. PLL centre frequency is set by R176(l). Outputs of counter, and ODD (odd/even track select) are decoded by PROM U62(l) to provide servo sampling clocks GA/, GB/. The stretched sync pulse from U65a(l) is fed to the shift register U67(l), clocked by QD from counter U63(l). Output of U67(l) encoded by gates U77a(l) and U77b(l) and applied to lower 5 inputs of Index control PROM U68(l). Remaining inputs come from counter U78(l), also clocked by QD. Counter is usually in state F, but is enabled by the PROM when Index byte 1 is found. Counter is also forced into state 8 by INX2/ signal from PROM when Index byte 2 found. Prom also detects missing sync, and removes Servo deterct/ if this occurs. Finally, PROM asserts State14/ if either index byte is found (when counter is in state E), anmd thus produces SINDEX signal via U77c(l). SINDEX presets sector counters U33(l), U42(l) and U55(l) to value set by jumper plug JX3. When counter rolls over, counter is again preset via U46d(l), and index | sector pulse is produced. U23b(l) provides a sector clock, decoded from the PLL circuit, to increment the counter. Also, U23a(l) is set if SINDEX has occured since the last counter roll-over, thus indicating the start of a new track. U34b(l) and U34c(l) decode the signals and produce the index and sector pulses. U43a disables the sector pulse coincident with the index pulse if enabled by W16 being removed. SA and SB are subtracted by the differential amplifier U31a(l) to provide the positioner error information, and then low-pass filtered (cutoff 10kHz) by U31b(l) to provide the POSX signal. This signal is inverted by U28a(l) to provide POSXN, and then reinverted (and offset) by U28b(l). Offset is controlled by R132. The resulting POS signal is fed to the motor control board. POSX and POSXN drive comparators U30a(l) and U30b(l), which switch when POSN waveform exceeds 80% of max in +ve or -ve direction. These signals are latchedd by U40(l) to provide PPL and NPL (+ve and -ve peak latched respectively), and fed to monostables U41(l). Outputs of these are ORed by U11a(l), and then fed to CPU as the Track Clock Signal. CPU resets latches U40(l) after track has been detected. Tracks are counted by the CPU to provide position reference. POS signal is applied to phase-shift circuit U21a(m) and U21b(m), which stabilises the servo loop, and then to the summing amplifier via switch U17(m), controlled by track follow signal TFM/. POS signal is also differentiated by Op-amp U7a(m) and then buffered by inverter U7b(m), to provide positioner velocity signal. Either normal or inverted signal cna be fed to velocity sythesiser via analogue switch U8(m). U8(m) is controlled by velocity control PROM U66(l), which produced S0/ - S3/ signals. S0/ controls time constant of velocity summing amplifier U9a(m). This signal goes low to shorten t/c when using differentiated position signal, and goes high for long t/c when using current signal. S1/ feeds diffentiated position signal into velocity circuit S2/ feeds inverted differentiated position signal into velocity circuit S3/ feeds IM positioner current signal into velocity circuit. Normally active (low). During peak of position signal, S0 switch opens, and U9a(m) behaves as integrator. PROM U66(l) decodes NPL (neg peak latched), PPL (Pos Peak Latched), Invert Slope (from CPU), Rev Direction (ditto), TP/ (Track Pulse), Velocity Enable (from CPU), Servo Enable (ditto), and Track Following Mode to provide signals to control velocity switches S0/ - S3/. PROM values encode the following velocity modes : 02 - POSX/ + IM 04 - POSX + IM 06 - Reset 07 - IM 0F - Hold IM signal is produced from positioner power amp by differential amplifier U26(m). POS signal is position error signal described above. VREF (velocity reference) is produced from DAC U74(l), via I->V convertor U75b(l) and selectable inverter U75a(l). It provides a CPU controlled velocity signal via U17(m), controlled by VFE/ signal. It also provides an offset in follow mode, via R69(M) and TFM/ controlled switch. VEL - the velocity circuit output, is fed into summing amp by U17(m) via calibration pot R71(m) and offset control R74(m) when VFE/ is active. When IMP/ is active, a larger form of the VLE signal is injected via R76(m) to stabilise the servo loop. IMP/ - inject vel signal to stabilse loop, and reduce setling time TFM/ - Enable track follow mode VFE/ - Enable Velocity feedback for head movement Common Output of servo switch U17(m) is fed to Op-amp U28a(m), which produces Error signal. By inserting W1, servo gain is incresed, allowing stability check. Summing node available on TP10 (and J2/4) for injecting position signals. Error signal is fed to 1050Hz notch filter U22(m), then to 1650Hz Notch filter U23(m). Output (SA) is available on J2/1, and fed to servo amp U25(m), where it is subtracted from IM signal. Output of U25(m) is level shifted by zener VR10(m), and applied to power amp U27(m), which drives positioned coil via retract relay K1. Drive signal is fed to positioner coil via Preamp cable and PCB Fault Detection --------------- Power supply fault : PSEN (from PSU on motor PCB) is filtered by U21a(l) and U21e(l) + associated components to provide the power OK signal. This signal sets the Fault flip-flop U57b(l) if the power supply fails. The output of this flip-flop becomes the emergency UNLOAD/ signal, and is combined with the Write Unsafe/ signal by U44c(l) to become the fault signal Spindle Fault: If the Speed OK/ signal goes high, the Speed OK signal from U21b(l) goes low. This interrupts the CPU via U34a(l), and the CPU then asserts the SET FAULT signal via U58(l) bit 3. This sets the fault flip-flop U57b(l). Servo fault : If servo detected/ goes high when the servo is enabled (servo enable is high), the output of U43d(l) goes low, and interupts the processor via U34a(l). The CPU then sets the fault flip-flop as above. Read/Write fault : RW Unsafe (from the PSU logic described above) sets the fault flip-flop via U44b(l). Write Unsafe fault : If Write Mode/ is active and the head is not on track, the 0 output of U48b(l) will go low, and the 1 output high. The latter disables the write logic, while the former directly sets the Write Unsafe flip-flop U57a(l). The output of U57a(l) is the Write Unsafe/ signal, and becomes the fault signal via U44c(l) Write Logic ----------- Incoming write data from the controller is converted to a TTL signal by the receiver U14a(l). The output of this receiver clocks the toggle flip-flop U13b(l), so that the flip-flop changes on each rising edge of the write data. The output of this flip-flop is converted to ECL levels by U12c(l). The outputs of this converter are applied to the differential amplifier Q6(l) and Q7(l) to produce the DX and DY head drive signals, which are fed to the preamplifier board. This amplifier is enabled by Q9(l) when Q4(l) is turned on. This occurs when PSEN (power Enable) and Wen (write Enable) are active together, detected by U20d(l). The write current is set by R45. The write head current is provided by the current source Q3(l), which is also enabled by Q4(l) as above. The current can be increased by turning on Q2(l) via Q1(l), which occurs when the Outer Track signal is asserted by the CPU. This happens when the head is over track 0 - 299. The head select signals (HSLT) from the interface register U26(l) are converted to ECL levels by U12a(l) and U12b(l). the outputs of these converters are fed to the preamplifier PCB. Similarly, the Chip select signals for the write amplifiers (CE1 and CE2) are buffered by U20b(l) and U20a(l) and fed to the preamplifier board. When WEN goes low, Q5(l) is enabled, thus supplying the 3.6V write select signal to the preamplifier PCB. Read Logic ---------- The output of the selected head preamplifier is fed up the DX and DY lines to the drive logic PCB. The heads are selected in the same way as for write mode above. This signal is connected to the read amplifier U1(l), where FET Q10(l) sets the gain, controlled by the AGC circuit. When the drive is in write mode, or seeking, the transient blank output from U44a(l) goes low. This signal enables the transistor Q12(l), and thus causes the Clamp/Analog signal to go positive. This signal forces the output of U2(l) high, and thus the RAGC signal goes towards 0. Thus Q10(l) clamps the inputs of U1(l). The output of U1(l) is similarly clamped by FET Q11(l) when the Clamp/Analog signal goes high. (Q11 is a depletion mode device). The output of U1(l) is buffered by the emitter follower Q13(l) and then filtered by the 2-stage LC filter L1(l) and L2(l). The output of the filter is then buffered by Q14(l). U4(l) acts as an equaliser, and thus improves the effective resolution of the read channel. The Inverting input is fed from the 100ns delay line DL1(l), while the non-inverting input gets not only the raw signal, but also a 200ns delayed version provided by a reflection in DL1(l), which is not terminated. These signals are attenuated by a T network, and then subtracted from the 100ns delayed signal by U4(l). This effectively reduces the read pulse width. The outputs of U4(l) are the EQ+ and EQ- signals. The output of U4(l) is buffered by the transistors Q15(l) and Q16(l), and then differentiated by the delay line DL3(l). This differentiated signal is then fed to the comparator U5(l), whcih consists of a cascaded pair of ECL differential receivers, to produce the Diff+ and Diff- signals. The Diff+ and Diff- signals are converted to a TTL signal by the converter U8a(l). The output of this converter feeds the edge detector configured from U9b-d(l). The output of this edge detector clocks the Pen signal (coverted to TTL by U8d(l)) into the read flip-flop U13a(l). This flip-flop is reset shortly afterwards by the delay network U12d(l), L10(l), C166(l), R224(l) and U8c(l), which thus sets the read pulse width. The output of the read flip-flop is connected to the line driver U10b(l), and is thus transmitted to the controller. The EQ- signal is used to produce the read threshold. It is buffered by Q17(l) and then delayed for 50ns by DL2(l). The output of this delay line is again buffered, bu Q18(l), and then fed to a pair of comparators, U6(l) and U7(l). These comparators produce a gating signal whenever the read signal is over 50% of the nominal amplitude, and the outputs, which are wire-ored together, provide the Pen (Peak Enable) signal to the read logic. The EQ+ and EQ- signals are buffered by Q33(l) and Q34(l) and then full-wave rectified by CR9(l) and CR23(l). The output of this rectifier is smoothed, and then buffered by U3(l), a unity gain buffer. It is then fed to the AGC summing amplifier U2(l), where it is added a fixed reference level from VR12(l), and 2 gain control signals, High Gain, which increases the gain via Q31(l), and low gain/ which decreases the gain by turning off Q32(l). The former is used to recover marginal data, while the latter is used in testing to ensure the drive is not becoming marginal. The Clamp/Analogue signal is also fed into this amplifier as described above. The output of the AGC summing amplifier is used to control the gain FET as described above. J10 (diagnostic) pins --------------------- 1 - gnd 2 - -12V 3 - Enable Low gain/ (to check for marginal operation) 4 - Reserved 5 - Diag Mode/ 6 - Reserved 7 - Write Unsafe/ 8 - Diag 1/ 9 - Diag 0/ 10 - VR1 11 - VR2 12 - VR3 13 - VR4 14 - VR5 15 - VR6 16 - VR7 17 - +5v 18 - +5v 19 - VR0 20 - Ready/ 21 - Power OK/ 22 - Fault 23 - R/W Fault/ 24 - Speed OK 25 - Lost Servo/ 26 - Diag 2/ 27 - Diag 3/ 28 - Set fault/ 29 - fault reset 30 - inhibit fault 31 - reserved 32 - analogue ground 33 - POSX 34 - Ground. Diag 0/ - Enable velocity calibration display (Must have Fault Inhibit true) Diag 1/ - Inhibit velocity calibration Diag 2/ - Offset track by additional 100microinches Diag 3/ - Not used. Error codes ----------- Sent on VR0-VR6. 0 - Reserved 1 - Spindle could not get to 250 rpm 2 - Spindle could not get to 2500 rpm 3 - Spindle could not get to 3600 rpm 4 - Servo could not find home band 5 - Servo could not find guard band 6 - Timeout in velocity adjustment loop 7 - Velocity scale factor overflow 8 - Seek timeout 9 - Positioner stalled A - Positioner did not settle B - Speed OK lost C - Servo Detected/ lost D - Positioner knocked off track. Test Points ----------- Motor Control PCB ----------------- TP1 - Power Ground TP3 - Analogue Ground TP4 - Vref (velocity reference from DAC) TP5 - Vel (Velocity signal) TP6 - Filtered position error TP7 - IM (positioner current) TP8 - Compensator TP9 - Position Error. TP10 - Error Summing node. TP11 - Velocity signal (differentiated POS). TP12 - Analogue Ground Motor PCB diagnostic connector (J2) ----------------------------------- 1 - Filtered Position Error 2 - Ground 3 - IM 4 - Error Summing Node (test signal) 5 - POS 6 - Vel 7 - Compenstator 8 - Position Error. Motor PCB Link -------------- W1 - Increase servo gain for stability test Logic PCB --------- TP1 - Analogue Ground 4 TP2 - EQ - TP3 - Differentiated EQ + TP4 - Diff - TP5 - Analogue Ground 4 TP6 - Analogue Ground 1 TP7 - Servo signal (SS) TP8 - Ground TP9 - Sync Pulse TP10 - Seek Complete TP11 - Sector Pulse TP12 - Index Pulse TP13 - ground TP14 - Stretched Sync Pulse TP15 - POSX TP16 - Rev Direction TP17 - Pull Up 1 TP18 - Read Data flip-flop TP19 - Ground TP20 - Velocity Reference TP21 - Velocity Reference Return TP22 - Ground Logic PCB Links --------------- W1 - Enable Remote Termination supply W2 - Termination Supply from +5V W3 - Select Drive 0 W4 - Select Drive 1 W5 - Select Drive 2 W6 - Select Drive 3 W7 - Enable Internal PROM in CPU W9 - +5V to Eprom pin 21 (for 2716) W14 - P23 to Eprom pin 21 W15 - P23 to Eprom pin 18 W16 - Inhibit sector pulse at index time W17 - Ground to Eprom pin 17 (for 2716) -------------