26 Jan
2009
26 Jan
'09
10:29 a.m.
Problem Solved!!!!!
I just thought I would drop a message onto the list, so it is
appropriately archived.
The root cause of my problem was a sloppy clock. All of the sample
schematics showed a crystal in parallel with 100K, in series with 1k,
with 27pF to ground. In a private email, Chris Elmquist provided the
actual 8073 data sheet, and there was a tiny little note indicating a
process change to XMOS, from NMOS, requiring that the 1k be dropped to
220R, and the 27pF cap be changed to 130pF. In short, I made those
simple changes, and the clock looked *much* nicer, and the board sprang
into life.
So, in short, there are no problems with having an address conflict with
low memory, a 62256 (32k x 8 RAM) can simply be selected using A15 as
the CS* signal.
Thanks everybody for the assistance, it has been very helpful. Ta
muchly!!!!!! By the way, my daughter thinks I am mad, what with 28K or
RAM...
Doug
Allison wrote:
--
Doug Jackson, I-RAP, MAIPM, MIEEE
Principal Information Security Consultant
EWA-AUSTRALIA
PO Box 6308 O'Connor ACT 2602
Level 1, 214 Northbourne Ave, Braddon ACT 2612
Tel: +61 (0)2 6230 6833
Fax: +61 (0)2 6230 5833
Mob: +61 (0)414 986 878
http://www.ewa-australia.com
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Subject: SC/MP
8073 addressing query
From: Doug Jackson <doug at stillhq.com>
Date: Wed, 21 Jan 2009 09:26:13 +1100
To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>
Hi list,
I have an interesting question regarding the INS8073 (National
Semiconductor SC/MP 3 with BASIC in ROM).
Finally, somebody gave me a round tuit, and I have started work on a
simple 8073 system.
Eventually, it will have 8K of ROM, 8K of RAM, an 8255, and a switch /
LED interface. Currently on the board, I have the 6264 RAM tied to the
8073, with no address decoding (ie the CS* on the RAM is tied to A15 on
the CPU). Sadly, as a simple test, this does not operate as I would
expect. I would have expected that the RAM would have been selected
anywhere in the lower 32K or the memory map, and I would have a simple
system that would spit out a console prompt. But no luck.
Now the question.... The internal ROM is located in the lowest 4K or
the memory map. When the CPU is fetching data from the lower 4K, does
it assert the NRDS line, and sample the external bus? My belief is that
it does not, as the trivial application note that I have seen simply
ties a couple of 2114 to the processor, and uses A10 as the chip select.
I built one years ago and pull it out frm time to time.
No, it's less than 4K and yes you do get NRDS.
Also you need pull up resistors on selected lines to set baus rate and
boot on rom.
I'd use 2116(2kb) or 2164s(8kB) as they are 8bits wide and really save
on parts and power over 2114. One 2164 placed at at 1000h makes for a
tiny sysem.
Finally NIBLE when it starts does a memory check for (Ep)rom at 8000h.
There are some addresses that are tested for information that have to
be respected.
If no one comes up with the circuit that National had for the demo board
they sold I can scan my copy, it's pretty poor but may help. The manual
is just too thick for me to scan or copy.
Allison
Any ideas?
Doug
--
Doug Jackson, I-RAP, MAIPM, MIEEE
Principal Information Security Consultant
EWA-AUSTRALIA
PO Box 6308 O'Connor ACT 2602
Level 1, 214 Northbourne Ave, Braddon ACT 2612
Tel: +61 (0)2 6230 6833
Fax: +61 (0)2 6230 5833
Mob: +61 (0)414 986 878
http://www.ewa-australia.com
============================================
IMPORTANT: This email remains the property of Electronic Warfare
Associates - Australia. If you have received this email in error,
you are requested to contact doug.jackson at ewa-australia.com or Ph
+61 2 62306833 and delete the email. This message is not to be
copied or distributed to other parties without the express permission
of the author. Any personal information in this email must be handled
in accordance with the Privacy Act 1988 (Cth).
============================================