PDP-8 core memory problems.

I'd tend to be more pessimistic about this working. There are different requirements in winding a wire for purposes of inhibit and sense. In the 3-wire arrangement the winding of the combined wire has to meet both sets of requirements. Specifically, for this case, in a 4-wire mem, where the inhibit wire was woven just for the purposes of inhibit, I don't anticipate it's going to have the noise cancellation topology needed to function as the sense wire. Sense wires were woven as a floating loop feeding a differential amplifier. The loop is kept quite closed or otherwise woven in a very balanced manner so that the magnetic fields from the large select currents (and other influences) will cancel out or be rejected as common-mode influence at the differential amp inputs. The select current magnetic fields trigger the magnetic field reversal of the core, you want to sense the latter distinct from the former. Unless you have circuitry with the wherewithal to distinguish those induced currents in the sense wire in time (delay of the core field reversal from the select field), you otherwise have to minimise the influence of the select current fields on the sense wire. If you look at the diagrams in my article you can see the sorts of differences in weaving topologies between 3 & 4 wire arrangements, as well as examples of the tortured topologies resorted to to balance the sense loop. In the 3-wire example there you can see how the S/I wire was split in half with a special resistor network at one end to allow inhibit current flow while at the same time configuring it as a balanced loop for the sense function. My article certainly isn't the last word on the variety of implementations, I believe there were 4-wire designs with sense wires parallel to select wires as in the 3-wire designs for example, so you never know until you examine the specifics at hand, but I think it unlikely you'd have much success getting the inhibit wire to function for sense, not without going to as much trouble messing with the stack as if you tried to fix the sense wire.

If the sense wire is open I'd guess there's a good chance it's at one of the end points where it's soldered to a terminal or at an existing splice from manufacture time and might be repairable if access could be had.

Might the stack have a parity bit array that could be redirected to replace the faulty bit array?, perhaps foregoing the parity checking on that board-set if the parity logic is present.