Tony Duell wrote:
With the
fastest CPUs being used today, that is becoming increasingly MUCH
more difficult. Tony, is that what you are concerned about as well, how the
logic analysers are able to keep up?
That is certainly a problem (it's one reason I don't have a fast
computer, I can't afford a fast enough logic analyser to maintain it),
but it's not the problem I was thinking of here.
I was thinking for farily traditional microcontrollers executing perhaps
20 million instructions per second at most. That is a rate that most
logic analysers can keep up with. But the problem is that if the
processor and program memory are on the same chip, there is no way of
conencting the analyser to the address and data buses so it can see
what's going on.
Thank you for the response. Over the years, I can't remember using a
logic analyser
more than two or perhaps three times. Since I usually work on projects
by myself,
I would not have had access to one. The last time, the fellow in charge
of the project
was not able to program, was was a whizz at electronics and could
connect the logic
analyser faster than I could see what he was doing.
In addition, over 90% of my work for the past 20 years has been on the
PDP-11
which has mostly adequate tools to debug the code, especially now with the
Ersatz-11 emulator which adds a very low level of breakpoints which are
able to
operate even to debug the very first instruction during a boot far in
advance of
any debug program being set up. Of course, the hardware ODT debug could
often help there as well, but not as conveniently.
As for your last point, your observation that when instructions and data
reside
in cache, a logic analyser is not going to be very useful is an aspect I
had not
ever thought about as a potential problem. INTERESTING!!
Jerome Fine