30 Jun
2014
30 Jun
'14
10:59 p.m.
On 1 July 2014 05:34, Jim Brain <brain at jbrain.com> wrote:
[...]
The test mode is engaged by placing 10V on the RESET pin.
[...]
So, I obviously am doing it wrong, but I can't
seem to determine where my
theory fails me, and I thought someone on here could help (or suggest
another simple way to support 3 voltages on the RESET pin under SW control.
Jim
Why not use Optoisolators? I assume per-unit cost is not an issue here :-)
Joachim
--
Joachim Thiemann :: http://jthiem.bitbucket.org ::
http://signalsprocessed.blogspot.com