1 Oct
2010
1 Oct
'10
9:28 p.m.
On 01/10/2010 8:16 PM, Chuck Guzis wrote:
On 1 Oct 2010 at 18:37, William Maddox wrote:
what race condition? Here I am thinking of simple ripple adder.
if you have no carry out, no problem.
if you have a carry, the carry must stabilize before you
have the start of the carry out propagate.
so a 1x delay is needed as the back of the envelope calculations.
Off hand I can't think of what gives over flow, the more important thing.
I am not sure exactly what you mean by a
"stable expression", but I
presume that your difficulty is in coming up with a purely
combinational formulation of the end-around carry, suitable for
execution in a single cycle, that seems suitably economical in logic.
Exactly--if you take a simple adder and send the carry-out to the
carry-in, you wind up with a race condition. You could clock the
circuit and run a second addition/increment based on the presence of
carry-out, but then you've got a synchronous adder with a delay of
either one or two clocks. If you're after an adder that operates
either asynchronously or synchronously in a specific number of
clocks, you have to settle for 2 clocks--one clock seems not to be
possible.
Thanks,
Chuck