Idle state for RAM-R/W (20) should HIGH (read).
I expect idle state for RAM-OD (18) is also HIGH (RAM outputs disabled).
I would suggest before trying to run a program you confirm that you
are able to load and examine memory.
One of the subtle points here is that when loading/examining/running
you generally need to go 'through' the RESET state with the mode
switches to reset the internal address pointer to zero.
Here's a load/examine test sequence:
Load:
L1 - set 2 mode switches for RESET (*RUN down, *LOAD down) (set 1802
address pointer=0)
L2 - set MEM-RD/WR switch for WRITE/LOAD (*MP down)
L3 - set mode for PROGRAM (flip *LOAD up)
L4 - set data switches to 0001 0000, press STEP/*INPUT (load $10 into
mem-0)
L5 - set data switches to 0001 0001, press STEP/*INPUT (load $11 into
mem-1)
L6 - set data switches to 0001 0010, press STEP/*INPUT (load $12 into
mem-2)
Examine:
E1 - set 2 mode switches for RESET (*RUN down, *LOAD down) (set 1802
address pointer=0)
E2 - set MEM-RD/WR switch for READ/EXAMINE (*MP up)
E3 - set mode for PROGRAM (flip *LOAD up)
E4 - press STEP/*INPUT, display should be 0001 0000 ($10)
E5 - press STEP/*INPUT, display should be 0001 0001 ($11)
E6 - press STEP/*INPUT, display should be 0001 0010 ($12)
If you miss step L1, you won't know where you are actually loading
into memory. If you miss step E1, the examine steps (E4,E5,E6) will
display addresses 3,4,5 rather than displaying addresses 0,1,2. The
same issue applies when running a program, you normally have to reset
state with the mode switches so the program starts running at 0.
I don't like the switch labels of the original Elf, they can be
misleading, but that's history. I relabelled/disambiguated them in my
schematic and unit, the * labels above are the original switch
labels, others are mine.
On 2012 Mar 17, at 8:48 AM, Gergely L?rincz wrote:
Getting there: finally I can see the hex result on the
display after I
press the input button. Seems to me that the control circuit work
fine.
However I tried to test the machine by entering 7b (SEQ) and
pressed INPUT
and set to RUN mode, expecting the Q output change it's state. It
didn't
happen:( The 1802the input and output section and the whole control
circuit
seem to work fine so I checked the RAMs. It seems that the read/write
enable and output disable pins (18 and 20) show different logic
state in
the two memory ICs. I assume this stops the instruction to be
entered to
the memory. Can you guys tell me what should be the state of pins
18 and 20
(output disable and write enable) in run and load mode and when
pressing
the input button? The datasheet doesn't have much info on this.
On 16 March 2012 18:15, Gergely L?rincz <alkopop79 at gmail.com> wrote:
> Problem (partially) solved: the LOAD switch stops the fliflop letting
> anything pass through until it's set on ( RESET mode). As if someone
> mentioned it that particular bit is wrong on the schematics. I
> assume i
> just have to rewire the thing.
>
> On 16 Mar 2012 00:51, "Gergely L?rincz" <alkopop79 at gmail.com>
wrote:
>
>> All of these test are done. Conclusion: if I remove the wire to
>> SC1 and
>> reset the 4013, it works fine, just as you described. In fact, I
>> spent a
>> few hours sending pulses from an Arduino (microsecond ones) to
>> simulate
>> SC1. I even managed to see the pulse from *Q* on the
>> oscilloscope. But
>> once the wire between the 4013 and the SC1 pin is used, nothing
>> works. I
>> even tried two different 1802s and they work fine (when the DMA
>> IN pin is
>> set low, SC1 instantly goes high). The only possible reason I can
>> think of
>> (since both the 1802 and 4013 works perfectly) is that one of the
>> diodes
>> are either broken or placed the wrong way around. An other thing
>> is that I
>> use a SPST button (input) instead of the SPDT. It still works
>> (for some
>> weird reason no SPDT buttons are rare and expensive in the UK).
>> I'll check
>> this tomorrow. The other mystery is that why the 4023 never sets
>> the HP
>> displays to enable mode. The displays are stuck (latched) and
>> even though
>> they work perfectly, the NAND gate (4023) never sets the enable
>> pins low. I
>> wonder if that has to anything with the previous problem? Anyway,
>> at least
>> I know where the problem is, even though I don't know what it is.
>> It's
>> certainly a good start! Thanks for all of your effort and
>> indispensable
>> help!
>>
>> Greg
>>
>>
>>
>>>
>>> Debugging trial: remove the connection from SC1 to the diode at
>>> the 4013
>>> reset (10).
>>> Now, when the input switch is released, nQ & nDMAIN should go
>>> low and
>>> STAY low as there is nothing to reset the 4013 (until you flip
>>> the load
>>> mode switch).
>>> It follows SC1 should go high and stay high or repeatedly pulse
>>> high as
>>> the 1802 is being held in the DMA state (which I think you
>>> already tested
>>> by forcing nDMAIN low).
>>>
>>>
>>>
>>>
>>>
>>