17 Jun
2011
17 Jun
'11
8:13 p.m.
On Fri, Jun 17, 2011 at 11:07 PM, Dan Roganti <ragooman at gmail.com> wrote:
I guess a basic way to describe is Negative Logic design is using a
different frame of reference.
Maybe a good analogy is whether you use RPN or alebra for your math.
Whether you're using TTL or ECL, the voltage levels are relative.
With Positive Logic, the True state, Logic 1 is a positive voltage relative
to the off state.
With Negative Logic, the Tru state, Logic 0 is a positive voltage relative
to the off state.
oops typo
So in the case of ECL, with a Vee of -5.2v the off
state is -0.8v which is
more positive than -1.8v
----------------------------------------------------------------^^^logic 0
level is
0.8v