PDP era and a question

While the thread has wandered far from the subject line, I am compelled to respond to some of this. Please Tony, this is not an attack on you. There is a lot of mis-information about FPGAs IP, software, and architecture. This thread has just exceeded my "sit back and read" threshold. Tony Duell wrote: This is ABSOLUTELY NOT TRUE. There is NO tool that can reverse engineer the bitstream to anything. Neither internal to Xilinx or external (and announced). There is ONE instance where the bitstream was "forward" engineered to find the mapping between design primitives and the resultant bitstream, and this was done by a company called Neocad, and they were acquired by Xilinx. The process they used did not have the capability of taking an existing design bitstream, and decoding this into any type of design database. The final translation from design database (NCD in current tools, LCA in prior generation) to bitstream is unidirectional. If you want to make changes to your design, you make them to the design database. If you desperately want to make design changes to the bitstream, Xilinx provides as part of the standard tool chain, LL files that point you to some but not all bits in the bitstream (LUT bits, and some FF bits. NO routing bits). Xilinx also provides a tool called JBITS, which can also modify the bitstream, and might be used to create a reverse engineering tool, but this has not been done to my knowledge. With regard to the "and announced" above, it is possible that an organization like the NSA may have done something like this, but they haven't told me about it. Even if such reverse engineering tool existed, you would end up with a CLB map, which I agree would be non-trivial to get into a useful schematic. While the research groups that weren't distracted by XC6200, and continued with the XC4000 and its descendants, have not wasted time screwing around with tools, and have gone on to do some real useful stuff. See the proceedings of the annual IEEE FCCM conferences. Flip-flop and LUT position in bitstream for an existing design: Directly avail in LL file. FF and LUT position for all bitstreams (alg for calculating it you self) Avail under NDA. Mode control, some more I/O info, but not routing info: Avail under a tougher NDA. The whole lot: Avail under a very tough NDA. This product has not been discontinued. At last report, Xilinx said that parts would continue to be available to anyone that wanted to buy them. Further development of the family has stopped. Further development of the support software has stopped, but that is not an issue, because you plan to write your own. see: http://www.vcc.com/RPU.html#anchor581456 status http://www.vcc.com/Papers/6200.pdf data sheet http://www.xilinx.com/techdocs/htm_index/utils_6200.htm Unknown. Data sheet is still available from http://www.vcc.com/Papers/6200.pdf and from Xilinx by request. Or maybe, they didn't sell enough. If the only people buying a chip is university researchers, in 1-10 piece quantities, it is not a viable product.