17 Jun
2009
17 Jun
'09
4:09 a.m.
----------------------------------------
From: cclist at sydex.com
To: cctalk at classiccmp.org
Date: Tue, 16 Jun 2009 09:42:52 -0700
Subject: Re: Intersil EPROM
On 16 Jun 2009 at 0:42, Scanning wrote:
Hi
I believe the critical step was self aligning source
and drain contacts. Until then, one needed a large
gate voltage to get the fields close to the contact
diffusion areas.
From then on, it has been mostly magic.
I work for AMD and help design these things and
I know it must be magic.
Dwight
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You are correct sir. I had forgotten about the
dark ages of 4000
Series 10 Volt Bulk CMOS. It's all coming back to me now, the night
sweats and the flashbacks.... I think I even have a 10 Volt CDP1802
lurking in a drawer somewhere...
I still have my "Solid State Scientific" reference manual for 4000
series CMOS--a slim booklet. Data for each device is displayed in 3
rows--for Vdd of +5, +10 and +15 volts. Performance at +5 was
ridiculous; propogation delays in excess of a microsecond for some
parts. Performance at +10 and +15 was *much* better. I conculded at
the time that, aside from the analogue switches, the family was
probably not ready for prime-time deployment at +5v. Considering the
speed and very low voltages that modern CMOS enjoys, the evolution
has been nothing less than remarkable.