27 Jul
2010
27 Jul
'10
1:37 p.m.
Very well designed buses (Unibus :-)) have each card send an interrupt
vector which directs the CPU to the right ISR.
I'm really getting off into
something I know absolutely nothing about
here, but I'm just curious as to how each card knows what interrupt
vector value to send? Jumpers/switches on each card? A "Unibus Interrupt Vector Value Guru" somewhere who
assigns the values? other
scheme?
In some machines (for example the Z80 peripheal chips), you write the
interrup vector into a device registor as part of the initialisation
(obviouslly before you enablae interrupts form that device) .
One others (e.g. HP's
This is a common way to do it...
If you want to drive a lot of serial channels it helps to have local
processing power on the serial cards. Some of the HP DIO serial cards had
Z80A CPUs and local buffer RAM on them, for example.DEC had their own
communcaiton processors (sometimes built from a lot of TTL...)
DIO-1 bus, the ISR has poll each card using that
interrupt level to see
if it's the source of the interrupt.
I've used an 8-UART RS232 card on
ISA bus under DOS that worked
something like that. It generated only 1 interrupt and the software had
to look to see which UART or UARTs caused the interrupt. Actually works
rather well if used judiciously. By judiciously I mean driving 8 modems
at not more than 33,600 baud worked really well. This was in the days
when a 386 was considered a really fast CPU too. :-) The ISA bus is
easy to design cards for (it's basically just the 80x86
bus) but it does have that horrible interrupt system. The idiot who came
up with the idea of active high, edge triggered, interrupt should be
condemned to spenmd eternity in a part of hades having to design complex
ISA cards and write drivers for them. He would then realise wby everyone
else used active low level triggering.
It has been a blessedly long time since I
had to write code to configure
a PIC (intel Priority Interrupt Controller) but ISTR they can be
initialized for either polarity and for either edge or level triggering.
What I don't remember is whether this could be done uniquely for each
IRQ input or whether it was a global setting for all 8 inputs to the part. I'd go look it up, but I don't want to
make my head hurt - - -
again. What I'm suggesting is that the guy who decided on high-going
edge-triggering may have been a software dummy rather than a hardware
one. :-) Totally different subject, but I figure there's gotta be a
special corner of hades reserved for whoever invented segment:offset
addressing as well...
Along with the people who added the logic for the upper 4 bits (or 8
bits) of a PC DMA address but didn;'t ahve any form of adder so DMA can't
cross page boundaries. ARGH!. The 8089 was a much nicer solution, but it
came too late for the IBM PC...
-tony