31 Dec
2008
31 Dec
'08
10:34 a.m.
On Dec 31, 2008, at 10:26 AM, bfranchuk at jetnet.ab.ca wrote:
Guy Sotomayor wrote:
I'd be looking at using 133MHz SSRAMs which are available in at least
512K x 36 (QFP - SMT). So you'd need 2 parts.
TTFN - Guy
As far as pricing goes, a 4 layer board (you
*really* want at least
4 layers here) + components + assembly & test should be < $1000.
How much less I don't know. The target for my unibus memory board
is ~$500 (fully assembled & tested + some profit). Given that this
wouldn't need unibus transceivers (hideously expensive when you can
find them) I would expect this to be in the same ball park
especially if it can be contained on a quad board.
The other issue with not replacing the cache, is
that the verilog
to implement this would *much* simpler (ie it can probably be
completed faster).
TTL ... and a few gals... I trust hardware more than software is my
view point.
Real cache memory 32k*8 is about 15ns access time in a skinny 28
pin package.
I am just not sure how much memory you can get on a card however ...
Sigh.