2 Mar
2012
2 Mar
'12
8:10 p.m.
On 02/03/12 18:26, Philip Pemberton wrote:
That's not strictly accurate. The DiscFerret has a
50MHz four-line High
Speed I/O interface.
OK, I hammed this. The bus buffer / level translator for the HSIO can
actually go as far as 100 megabits per second (min pulse width of 10ns).
The guaranteed specification for the DiscFerret is a 50Mbps signal.
The chip in question is the TI TXB0104. Datasheet SCES650E, page six,
"Timing Requirements, Vcc_A = 3.3V".
It's also worth reading "Switching characteristics, Vcc_A=3.3V,
Vcc_B=5V" on page eight of the same datasheet.
--
Phil.
classiccmp at philpem.me.uk
http://www.philpem.me.uk/