Date: Mon, 6 Jan 2014 06:18:59 -0800
From: aek at
bitsavers.org
To: cctalk at
classiccmp.org
Subject: Clocking (was Re: RFC Ethernet Bus Interface V1)
On 1/5/14 8:08 PM, Philipp Hachtmann wrote:
You don't need such a big project with many
strange cores to get the understanding. Understanding the digital stuff is SIMPLE.
I've been designing digital logic since the 70's. Wrapping my head around someone
else's large project, be it in a HDL or some hairball of C++
out of a SVN repository is the problem :-)
Understanding digital stuff IS simple, if you have a single clock domain. Looking at how
large blocks of logic are clocked is one of the first
thing that I look at. Understanding how the DECtape interfaces work again has been fun.
Think about building a peripheral interface where your
input clock varies +/- 10%
---snip---
Reading Verilog or HDL that two different people have written where
they've switched from positive to negative logic and back is a pain.
Dwight