PDP-11/70 debugging advice

On Sun, Jan 31, 2021 at 7:04 PM Fritz Mueller via cctalk < cctalk at classiccmp.org> wrote: I was just looking in chapter 4 of the processor manual to learn more about how the processor clocks are generated on the M8139 (TIG) board; on page II-4-2 (p. 136 in the PDF on Bitsavers) section 4.1.3 it says: "The third source of timing [the other two being the crystal clock and a diagnostic R/C network] is the manually-operated, single-step MAINT STPR switch S4, located on the maintenance card. This switch is only enabled when maintenance card switches S2 and S3 are both set to 1." Section 4.2.3 confirms this: "The maintenance card S2 and S1 switches are both set to 1 to allow single timing pulses to be generated by MAINT STPR switch S4.... Removing the S2 or S1 input conditions the MS EN flip-flop to be cleared." Well, what's interesting here is that on my system, switch S4 (MAINT STPR) steps the processor with switches S1 and S2 set to *any* configuration. Tried it with the other KM11 I have, same behavior. This being the case, I wonder if the logic that selects the clock source is faulty, and is always selecting the MAINT STPR input. This would definitely explain the behavior I'm seeing. I hope the fans arrive tomorrow so I can start debugging this :). - Josh