14 Jan
2013
14 Jan
'13
1:51 a.m.
On 13/01/13 8:16 PM, Richard wrote:
...you'd have to do an actual end-to-end analysis
to see
how fast you could update the AEd from a Qbus PDP-11; the DMA transfer
rate may not be the limiting factor.
You'd have to halve the rate in any case since the CPU would take an
equal amount of time doing memory cycles to update it? Correct me if I'm
wrong, but the frame *computation* would be concurrent with the DMA but
updates from the CPU would be sharing the bus, interleaved with
individual DMA cycles, and you couldn't feasibly do block DMA (because
of that concurrency).
It seems to me this isn't a very natural fit for DMA?
--Toby