2 Jun
2019
2 Jun
'19
11:34 a.m.
Sorry for the break, finals at school have been a little crazy. For
simplicity of testing I have switched back to the M8017-AA instead of the
M8043. The both are behaving in the exact same manner, so I am not ruling
out the idea that the CPU is at fault just yet.
On Wed, May 29, 2019 at 6:17 AM Noel Chiappa via cctalk <
cctalk at classiccmp.org> wrote:
I suppose it would be worth while checking BDALn,
BSYNC and BDIN _on the
console card_ (I'm not sure where he was looking at them, before) just to
rule out the broken bus line possibility.
I took a look on them, all of the signals make it into the card
On Tue, May 28, 2019 at 9:08 PM Noel Chiappa <jnc at mercury.lcs.mit.edu>
wrote:
Hey, I have some extra console cards; probably the
best thing to do at
this point is to send you a known working (i.e. tested) one. You can
then send me back your broken (maybe?) card - I don't mind getting a
broken one in trade, I can amuse myself fixing it.
If you'd like to try this, let me know your mailing address, and I'll
get a tested card off to you (once the tree craziness dies down).
Sorry you're not up and running yet... :-(
Noel
Thanks for the offer, but I think I can diagnose if the card is working
properly pretty easily. Looking at the schematics for the M8017, the BRPLY
signal is generated by the 4 DC005 and DC004 (or DC003, I can't remember)
chip. The bank of DC005 chips compare the address coming in with the
address defined by the jumpers, and the DC004 takes some of the other
signals on the backplane and combine the MATCH signal from the DC005s to
generate the BRPLY signal. I should be able to find if the correct signals
are coming in by looking at my logic analyzer, and then use that to see if
the DC005s are generating the MATCH signal.