19 Jun
2008
19 Jun
'08
12:10 p.m.
Eric J Korpela wrote:
On Mon, Jun 16, 2008 at 1:58 PM, Eric Smith <eric
at brouhaha.com> wrote:
for the discussion there is minmally z80a (2.5mhz) for timing for FDC loops.
The faster 4,6,8 and 10mhz parts can solve the issue with brute force speed.
Allison
With a Z80 a typical read transfer loop takes a
minimum of 52 clocks,
which on a 2 MHz Z80 meets the requirements for all but 8" double density,
which requires a faster processor, DMA, or special tricks.
Having missed the first part of this discussion, are we limiting ourselves
to a Z80? If not, I'd nominate a Z80A or Z80B.