On 21/05/2007 21:41, Johnny Billquist wrote:
Okay, since this topic have become a subject of much
discussion and some
diverse opinions, I decided to really read the manuals to try to find
the bottom of this all.
So did I :-)
Now, to start with the position of the CPU card in an
11/84.
Chapter 7, section 7.2. Page 7-1:
"7.2 PMI INTERFACE
[...]
The LSI bus signals that are used
with the PMI protocol use the A and B rows of the backplane defined as
the LSI bus."
Well, just before we deal with the CPU position, didn't you notice that
the above says it uses the LSI bus? That is, it uses QBus :-)
Now, if Pete is correct in that the PMI bus on the
11/84 really goes to
both pins on all slots, then it should be okay to place the CPU in any
slot. I haven't tried that, but I might when I have the time. I suspect
he's right since otherwise I would have expected the CPU to be in slot
3. But DEC could be doing some fancy wiring... :-)
No, I knew they hadn't done anything fancy because I'd checked the
wiring diagram for the backplane. Still, it's not exactly true that you
can put the CPU in any of the top slots equivalently. This evening I
remembered the SRUN L signal which drives the RUN light, and it's only
connected to slot 1 in an 11/84, at least in the backplanes I checked
the wiring for. If you don't care about the light, put the CPU in any
of the QBus slots :-)
As for wether Q-bus memory (or any other Q-bus
peripherial) will work,
I'll quote some signal descriptions.
Chapter 7, page 7-4. Table 7-3 PMI Unibus Adapter Signals
"Pin: CF1 Mnemonic: PUBSYS L PMI Unibus System
In a Unibus system, PUBSYS L is asserted by the UBA to direct the
KDJ11-B to follow PMI protocol for all data transfers, wether the PSSEL
L is asserted or not. LSI-11 bus protocol is disabled for all PMI
devices when PUBSYS L is asserted.
But is that asserted all the time? I see nothing to say so.
Chapter 7, page 7-5. Table 7-4 LSI Bus Signals
"Pin: AF2 Mnemonic: BRPLY L Reply
During PMI cycles, BRPLY L is asserted by the KDJ11-B and the PMI slave
to prevent the next bus master from gaining control of the bus too soon.
In a Unibus system, BRPLY L is asserted by the UBA as a slave response
during the PMI DATOB cycle and interrupt DATI cycle.
So?
Pin: AH2 Mnemonic: BDIN L Data Input
The BDIN L signal is only used in PMI Unibus systems during interrupt
grant cycles. The KDJ11-B asserts BDIN L after it gates the interrupt
priority, BDAL bits <3:0>, onto the bus. The UBA then latches the
interrupt priority data using the leading edge of BDIN L.
Of course, if you have a PMI memory, you don't use BDIN, you use PRDSTB
instead. That doesn't mean it won't work if you start a non-PMI bus
cycle. The writer was simply assuming that everything not on the Unibus
side was using PMI, and therefore wouldn't use BDIN. It doesn't mean it
can't be used.
Pin: AM2 Mnemonic: BIAKI L Interrupt Acknowledge
In
Pin: AN2 Mnemonic: BIAKO L Interrupt Acknowledge Out
These signals are only used in PMI Unibus systems during the interrupt
grant cycles. The KDJ11-B asserts the BIAKI L signal, and the UBDA
acknowledges it by asserting one of the Unibus bus grant signals.
Well, of course. So what?
Pin: BB1 Mnemonic: BPOK H Power OK
This signal is only used in PMI Unibus systems for the Unibus
power-up/power-down protocol. This signal is asserted and negated by the
UBA in response to the Unibus AC LO signal. The assertion of AC LO may
be prolonged by the Unibus devices or the PMI memory during power-up."
Again, there's normally nothing else in these systems that would want to
use it. All that says is that the only thing DEC put in, that cares
about it, is the power up/down logic. Just like QBus.
I could go on describing more details on how these
signals are used,
since it's all described in the manual.
You could, and so could I :-)
Now, can we now accept that it's not a Q-bus in
the 11/84? :-)
No. There's still a QBus, even if the system normally uses PMI
protocol. You think it's omnibus? ;-)
--
Pete Peter Turnbull
Network Manager
University of York