Carlos Murillo wrote:
Again, Itanium is more or less what HP already had in sight as a
replacement/successor to PA-RISC even before it was called
Mercer/IA64/Itanium. HP had intended the architecture to
feature many parallel resources (which IA64 will have), multi-instruction
set with dynamic switching (which IA64 will have) and
a sophisticated instruction scheduler that would have optimized
the utilization of the chip resources to achieve maximum parallelism,
instead of relying on the compiler to do the optimal scheduling.
HP holds patents on all of these features. When the alliance with
Intel came up, they dropped the last feature from the design
and went back to the schedule-optimizing compiler paradigm. I am sure
that Intel then pressed to include features that they deemed
"convenient". In any event, Itanium is more a brainchild of HP
than of Intel.
And now with the help of the alpha crew, they can clean up the Si mess
they made,
put the instruction scheduler back in, and finally get this EPIC
working,
but now as an OOO EPIC ;-)
Anyway, we should postpone this discussion for another ten years,
when the subject becomes vintage.
Let's see how many people remember than, what merced or itanium were ...
cheers