13 Nov
2007
13 Nov
'07
10:37 p.m.
In the CDC 6600, I should probably say that Seymour
Cray rigged
things to give the *appearance* of 10 PPUs. Core back then was 1
microsecond and the CPU used it interleaved by a factor of 10, so a
cycle time of 100 nsec was possible. The "10" PPUs all shared a
common ALU--each had its own 1 microsecond 4Kx12 bit memory, P-
counter and accumulator, and each took a turn in the "barrel" so that
each appeared to be an independent CPU. Access to central memory (60
bits wide) by the PPUs was obtained through what was called the "read-
write pyramid" where up to 5 CPU words could be in various stages of
assembly or disassembly. It was very slick.
Low end IBM mainframes also used this trick, stealing the ALU away
from the processor to do channel stuff. It is almost
like the
processor emulated the channel you were too cheap to buy.
--
Will