That darn Intel jingle...

I avoid Intel chips for a much more practical reason -- they often have some of the most amazing misfeatures you'll ever see.... The worst, by far, has to tbe the 8255 parallel chip. That was clearly designed by soembody who didn't think what he was doing. For those of you who've not read the data sheets, any write to the mode control register clears all output port lines to 0. Doing anything to the output registers when writing to the mode control register is bad enough. But setting them to 0 is about the worst thing that could be done. On reset, all port lines are inputs (sensible, it avoids a possible contention). Rememebr a TTL input floats high, so TTL inputs connected to port lines will appear to be logic 1. Then you write to the mode control register, and all lines you want to be outputs will be logic 0. Then you write to the ports to set them to the right values. You have to design a circuit that can cope with the steady 1 after reset and the 0 after writing to the mode control register. Sensible poarallel interface chips (Motorola, Rockwell, etc) let you initialise the output registers and then set the mode/direction. In otehr words you can keep a port line effecrtively at logic 1 throughout the initialisation. But yes, that jingle is so darn annoying... -tony