Tony, could the 1802 be in LOAD mode (CLEAR low, WAIT low)? You'll
get DMA-IN cycles in that mode.
"LOAD: Holds the CPU in the IDLE execution state and allows an
device to load the memory without the need for a "bootstrap" loader. It
modifies the IDLE condition so that DMA-lN operation does not force
execution of the next instruction."
--jc
Tony Duell wrote:
Oh, also the
SC0/SC1 states are only valid on TPA. Does your datasheet
call that out?
Thanks, no I'd not spotted that. Tomorrow (it's getting late...) I will
see (a) which states it is going into and (b) if the pulse on SC1 occurs
coincident with TPA. And so on.
-tony