The idea is to get timing accuracy - down to the logic block level. If
I run the system "oscillator" (which is really a clock divider on the
FPGA development board clock) at the same speed as the original, then it
should run at pretty much the same speed as the original - much MUCH
slower than it would be using software emulation on a modern machine.
JRJ
On 5/2/2021 5:51 PM, Chuck Guzis via cctalk wrote:
That's a very ambitious project! I commend you
for your determination
and thoroughness.
I am a bit curious, however. How does this implementation (other than
perhaps speed) compare with a software emulation done on a modern CPU?
--Chuck