segmented memory models

On 1 Aug 2008 at 20:47, Fred Cisin wrote: It seems to me that Intel was attempting to solve two problems with the 16-byte segment + offset addressing. The first, and likely most important in Intel's mind was to afford addressing of more than 64K bytes. The second was to give some sort of location-independent facility for addressing code and data. Recall that in the 808x, all addresses are absolute, with on-the-fly relocation a reall PITA. The 8086 gives one the capability of position-independent code and data, at least to a granularity of 16 bytes. The downside is that when addressing a structure of more than 64K in size, address computation gets a little too involved for my taste. I think that a couple of special-purpose segment+offset arithmetic instructions might have helped quite a bit. Intel certainly could have used its segment registers as 64KByte- sized address pointers, but then the relocatability aspect would have suffered at the expense of simpler segment arithmetic. I think it's important to keep perspective here. The 8086 dates from 1978, only a year after the 8085. It was never intended to be the end result of 16-bit development at Intel, but a placeholder until the 432 "micromini" could be deployed. Moto deployed the 6809 a year later in a similar role-filling mode, the difference being that the 68K was a winning design, where the 432 fell on its face, leaving Intel with the x86. Back around 1977, there was a lot of chatter about "16 bitters". One of the big issues for systems designers was the company behind the chip. National was horrible in terms of support (PACE). TI (TMS9900) wasn't much better. GI seemed to be disintrerested in its CPU (CP1600). DG didn't want to talk to people who might compete with it (MicroNOVA) and Fairchild was loathe to admit that it even sold the 9440. All of the above suffered from one problem--64K address space size. Cheers, Chuck