18 Aug
2006
18 Aug
'06
3:08 p.m.
Tony Duell wrote:
I am not sure, and the service manual (which I have) doesn't make any
obvious reference to this.
Any timing diagrams for DRAM access? You'd recognize the page mode
cycles by the lack of a 1:1 pairing of RAS with CAS.
It's probably possible to add external circuitry
to turn that back into a
normal 18 bit address and hang SRAM off it, but I think it's more work
than finding some 41256s...
I would assume the controller would exploit page mode
references
(especially when dealing with sequential accesses like video).