If a tristate
buffer is enabled by its control line, but the input
to the buffer is at high-Z is there a typical output?
High, but with less noise
immunity then if you tied the input high.
The immunity could vary with the TTL family, but leaving unused
inputs floating was standard practice with "standard" TTL, for
instance.
Yes - but note that the chip may not be TTL. The message said
SN74ABT241As, and I think ABT is one of the recent "TTL-compatible"
families, logic that can be connected directly to TTL power and signals
but not actually TTL. Thus, while TTL inputs do generally float high,
that may not be relevant to 74ABTxxx chips. (It also may; I don't know
enough details of the 74ABT input structure.)
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