22 Jul
2016
22 Jul
'16
5:10 p.m.
It's not.
Peter is talking about a four-bit field in the
instructions. You're talking about a six-bit field in the program
counter.
Something that's always bothered me about three-address architectures
like ARM is why there is the insistence on that scheduling bottleneck,
the condition code register? You can see how two-address architectures
like the x80 and x86 try to get around the problem by having certain
instructions not modify certain condition code bits and even have
specialized instructions, such as JCXZ, that don't reply on a specific
condition code.
... bdnz, which decrements CTR and branches if not zero, ...
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