OT? Upper limits of FSB

On Tue, Jan 8, 2019 at 3:01 PM ben via cctalk <cctalk at classiccmp.org> wrote: Even worse than you might think. For user mode code you've got at least two context switches which are typically thousands of CPU cycles. On the plus side when you start waiting for I/O the CPU will execute another context switch to resume running something else while waiting for the I/O to complete. By the time you get back to your process, it's likely process memory may be at L3 or back in main memory. Depending upon what else is going on it might add 1 to 50 microseconds per I/O just for context switching and reloading caches. Of course in an embedded processor you can run in kernel mode and busy wait if you want. Even fast memory mapped I/O (i.e. PCIe graphics card) that doesn't trigger a page fault is going to have variable latency and will probably have special cache handling. -- Eric Korpela korpela at ssl.berkeley.edu AST:7731^29u18e3