Floppy disc reader/writer status report

It's done. $DEITY-knows-how-many hours of effort, and it's *finally* done. Of course, I'm referring to the CPLD that drives the disc reader. All the logic has been bolted together, compiled, synthesized and fitted into a Xilinx XC95288XL-10 CPLD. I haven't run the test suite on it yet, but it passed the timing analysis with a theoretical (emphasis on THEORETICAL) maximum clock rate of 71.429MHz. Meaning it's sure as heck going to run fine at the 32MHz I wanted to run it at, with a >2x safety margin. Which is quite nice, actually. I still need to fiddle with the pinout and lay out the PCB, but once that's done I can try and build up a prototype and have a play with it. At some point I'll need to order a couple of XC95288XL chips from Digikey, the shipping charges from which are going to utterly obliterate my 'buy a new lens for the 400D' budget... Here's the stats, for anyone that actually cares: ----- cpldfit: version J.33 Xilinx Inc. Fitter Report Design Name: floppyrw Date: 5- 7-2007, 9:11PM Device Used: XC95288XL-10-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 223/288 ( 77%) 1243/1440 ( 86%) 615/864 ( 71%) 146/288 ( 51%) 50 /117 ( 43%) ----- The CPLD code is zipped up at <http://www.philpem.me.uk/temp/floppyrw.zip> for anyone that wants to take a peek. It's nothing really special, and floppyrw.v is a huge mess, but it should give you some idea how it all works. I've tested everything except the top-level module. You'll need some version of Xilinx ISE (I used WebPack 9.1i) to compile it, and some knowledge of Verilog HDL to modify it. Have fun, -- Phil. | (\_/) This is Bunny. Copy and paste Bunny classiccmp at philpem.me.uk | (='.'=) into your signature to help him gain http://www.philpem.me.uk/ | (")_(") world domination.