26 Jun
2010
26 Jun
'10
2:11 p.m.
Johnny Billquist <bqt at softjar.se> wrote
You do know that the J11 is already designed for mP
usage, except that
DECs testing of that was even more secret than the 11/74?
Sure, the mP instructions WRTLCK and the TSTSET of the J11 are
documented, and allow cleaner way to implement spin locks than
the 'asrb hack' of the 11/74. In a future version of the w11a I'll
probably also implement the instructions supported by 11/34 and
J11 and make the 'processor profile' selectable at start time, much
like in the simh simulator.
But FPP is among the most important things in there as
well, I'd say.
Lots of software who won't be happy without it.
That's true from a performance point of view. However
- you can run RSX and Fortran without FPP (did this 30 years ago
when the FPP broke on the 11/45 I was working with...).
- you can run 2.11BSD without FPP (I'm doing that each time I
boot 2.11BSD).
So a FPP is very good to have, but not my highest priority. Also,
it's quite a project to design, implement and verify it, with the
verification, as usual, being the most time consuming part.
By the way. You don't have to worry about cache
coherency. The
PDP-11/74 do not do that. Cache coherency is managed by software
on the PDP-11 (well, in RSX, since that's the only system that
supports the hardware). In short, the real hardware do not implement
any sort of cache coherency in hardware.
I know, but I'll go for a cache with full cache coherency. That will
make it a lot easier to try a MP hack for 2.11BSD. And RSX, if I ever
get to it, will not mind.
Walter