Skip the memory bus and the original cache. The
original cache is
just 2 KB
of 2-way associative memory. If you set up a 4 MB cache, the CPU
can run at
full steam the whole time, with a cycle time of about 150 nS, if I
remember
right.
Handy, since 70ns SRAM is easy to find.
It is more complicated, though. You'll have
access paths from CPU,
Unibus
and four massbus controllers to deal with. But it should definitely
be
doable (heck, SETASI have already done it once).
I might be interested in such a project myself, since the 11/70s we
have
around here still are on MK11 boxes. I could deal with PCBs and
design, but
I'm very short on time, as usual... :-(
No experience at all with FPGAs or any such fancy stuff.
If such a thing were to be designed (I could participate in the design
phase, but not drive it), I'd probably be interested in two,
especially if the blank board was only a few hundred dollars. If it
came closer to $1000, I'd really have to think about passing on the
second one (I used to order multi-layer DEC backplane boards, and at
the time, $500 was a good price for orders between q10 and q100, but
things in the PCB market have changed radically).
I'm in no hurry - my 11/70s are in storage and I won't be able to even
pull them out to look at them in the next 90 days.
The problem with replacing the cache is that it is composed of 4 hex
boards (M8142, M8143, M8144 and M8145). I haven't looked at the
backplane signals, but I'm dubious that it could be done with less.
The advantage of just replacing the MK11 boxes, is that it could be
done with just one board. Depending upon signaling and such (and with
sufficient integration - ie FPGAs and SMTs) it *might* even fit on a
quad board vs hex.
As far as pricing goes, a 4 layer board (you *really* want at least 4
layers here) + components + assembly & test should be < $1000. How
much less I don't know. The target for my unibus memory board is ~
$500 (fully assembled & tested + some profit). Given that this
wouldn't need unibus transceivers (hideously expensive when you can
find them) I would expect this to be in the same ball park especially
if it can be contained on a quad board.
The other issue with not replacing the cache, is that the verilog to
implement this would *much* simpler (ie it can probably be completed
faster).
TTFN - Guy