1 Mar
2015
1 Mar
'15
3:13 p.m.
On Sun, Mar 01, 2015 at 09:59:12AM -0800, Al Kossow wrote:
It makes sense on machines with a single word order
code. Incr instruction
pointer by one and you're done. It makes much less sense on multi-word order
codes where you have to crack the instruction to see how far to advance the
instruction pointer.
OK, true story time. Those who have been around computing for a while
will be able to put a pretty close range on my age with this one.
My _second_ computer was a PDP-8. Remote timeshared. IIRC an 8/M.
I _do_ remember what happened when the 4th user logged in: (nothing)
It was usable with 1 or 2 users.
But my confusion was the assembler manual. I looked at the example
listings and thought "but how does it know in what order to execute
the instructions?"
You see ... my *first* machine was a Bendix (although late enough to
be labeled Control Data) G-15. Those have drum memories. 29-bit
words, too. And, due to rotatinal latency, the address of the next
instruction is _contained_ in each instruction.
You can imagine the games that were played to optimize (and, in a few
specific use-cases, pessimize) access time over an instruction stream.
I think it took me a good 30 minutes to puzzle out "oh, I guess they
just use the next instruction in the sequence."
(Yes, I already understood test-and-branch operations. I mean, other
than that.)
mcl