12 Mar
2016
12 Mar
'16
10:33 a.m.
On Sat, Mar 12, 2016 at 10:27 AM, Dave Wade <dave.g4ugm at gmail.com> wrote:
Copied back to the main list?.
OK on the L66 machines I worked on we always kept the doors closed, there
was an application, can?t remember its name, we ran on a VDU by the system
console that displayed the Job Queues, State of Active Jobs, CPU
utilization etc. There was also a MIPS meter on the console. They were very
modular, and as the store was in the SCU?s on a multi-cpu system you also
needed cross coupled cache cables to invalidate the CPU cache when the
other CPU overwrote a word in main sore that it also had cached.
I think the cross-coupled cache cables post-date the code and documentation
I have; I believe that Multics does a inter-CPU interrupts to do cache
invalidation.
SInce the emulator doesn't implement the WAM cache, cache coherency isn't a
problem, and one of my low priority projects is determining if Multics can
use the knowledge of no-caching to to reduce overhead. (Ie. don't signal
invalid cache.)
Interleave was also interesting, so you could
configure interleave memory
word by word so alternate accesses went to the ?other? SCU. A guy we had in
at NERC Bidston (was www.pol.ac.uk), Vince Martin I think his name was
who had worked in the Honeywell performance labs, I believe in Scottsville.
Arizona said this would give much better performance. He also said the big
bottle neck on the L66 was memory bandwidth. With the fast 6250 BPI tapes
he said the tape drives could drive the memory flat out, locking the CPU
out?.
I believe that.
-- Charles