18 Dec
2008
18 Dec
'08
11:16 p.m.
You can emulate that in std_logic with a single driver
driving an "H"
(the "pull-up"), and everyone else drives either "0" or
"Z".
Yes. You can write that. But the synthesis tool - if it eats that -
will generate
many ORs... So avoid it. In the company I have worked a bit for, MANY constructs
were simply forbidden. Thinks like Z, H, L in std_logic are suspicious :-)
VHDL.
Nice. I like it, too :-)
Using Xemacs' VHDL mode. No, I'm trying to re-express everything in a few
clock domains, namely
the timing pulses at the beginning of the cycle. The rest goes in the
combinatorial part of the thing:
Timing pulses come at the END of a timing state!
TS1 is the state, left with TP1...
if (tp4'event and tp4 = '1') then
fetch <= f_set;
defer <= d_set;
execute <= e_set;
word_count <= wc_set;
current_address <= word_count;
break <= b_set;
end if;
That's sequential coding!!
So I will see how you get it working your way. Everybody has his/her own way :-)
I once thought of a gate level transformation of the Honeywell H316 into an FPGA.
That's even more
difficult: Nearly the whole machine is built from NAND-gates :-)
So they have really cool things like a flip flop with many OC gates pulling it down. And
no clock at
all, only transport pulses...
Philipp
--
http://www.hachti.de