On 12/22/13 8:43 AM, Al Kossow wrote:
Here is a first draft. Anything wrong/missing
architecturally?
The one thing that I didn't think of was not handling 18 bit data transfers
on Unibus DMA, though now that I've thought of it adding the data parity bits
to the buffering wouldn't be a big deal even if there wouldn't be any code
behind it.
That is only an issue for two systems I can think of, KS10s and Unichannel-15s..